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276 | Alrudainy, Marzook, Hussein & Shafik
TABLE I.
LIMITATIONS AND FEATURES OF THE PRESENT APPROACHES
Reference Architecture Verification Design Platform Key of Novelty
abstraction
[7] Power gating,
Homogeneous Hardware system Not specified Task mapping
[8]
Homogeneous Hardware Micro- architecture ARM Sub-clock
[9] Cortex-M0 Power gating,
Power gating,
[10] Homogeneous Hardware system Intel Core I7 (Turbo boost)
Power gating,
[11] Homogeneous Hardware system AMD Opteron 6168 manually adjusted DVS
[12–16] Low complexity,
Heterogeneous Hardware system Odroid-XU3 Realtime+DVFS+TM
[17] Realtime +DVFS+TM
Proposed Heterogeneous Hardware system Odroid-XU3 Power modelling
Heterogeneous Simulink ( Gem5) system ARM Cortex-A15 PCPG based WLC
+DVFS+TM
Heterogeneous Hardware+ system Odroid-XU3
Simulink (Cadence)
compared to the homogenous cores counterparts. To alleviate power gating (PCPG) based workload classification (WLC)
the trade-offs between energy consumption and throughput performed on Samsung Exynos 5422 heterogeneous mobile
a common approach is to assign heterogeneous computing system to be a novel effort. In our proposed approach, the
resources (cores) on these platforms. Contemporary platform following major contributions has been made:
such as Samsung Exynos 5422 big. LITTLE octa cores sys-
tem, which comprises 4 LITTLE (ARM A7) cores, and 4 big • propose a per core power gating (PCPG) approach for
(ARM A15), is a reasonable choice of illustration in this work. contemporary heterogeneous mobile platform based on
workload classification to effectively support various
Over the past few years a substantial research has been workloads,
conducted to meet energy cost reduction in heterogeneous
embedded mobile platforms such as those from Arm and In- • core of the approach is an integrated power saving man-
tel [11–14] [18–20] . Such efforts normally manage dynamic agement for dark silicon area based on workload clas-
voltage frequency scaling (DVFS) decisions, combined with sification metrics, modeled adopting the performance
the core allocation to threads to respond to workload varia- counters feedback,
tions. For instance, when a higher workload is experienced
more number of cores are assigned with appropriately chosen • validate by means of various type of real application
DVFS combination. On the other hand, when a lower work- benchmarks to illustrate reasonable superiority and
load is encountered, fewer cores are allocated with decreased trade-offs.
DVFS combination.
The rest of the paper is structured as follows. Section 2
Although DVFS coupled with core allocation (TM) play a limitation and features of the present approaches are exten-
significant role in minimizing dynamic energy consumption sively explained. The system architecture and application is
in contemporary heterogynous many core systems, dark sili- comprehensively described in Section 3. Workload classifica-
con contributes to significantly unuseful power consumption, tion metrics obtained from performance counter, and PCPG
principally decreasing the battery operating active time. To de- control decision based on workload classification details have
crease the dark silicon energy consumption, power gating tech- been demonstrated in Section 4. The proposed approach is
nique was adopted in many recent published research [7–10]. expansively discussed in Section 5, deals with per core power
The fundamental key is to utilize a layer of sleep transistors gating management and power switch network. Section 6
to shut down the inactive cores by disconnecting the power discuss the results of the experiments, and, lastly, Section 7
supply voltage. In this paper, we propose a novel per power provides the conclusion the paper.
gating technique combined with DVFS and thread to core
allocation in order to drastically decrease energy consump- II. RELATED WORK
tion. To the best of our knowledge, we consider that per core
Energy efficiency of many-core mobile platforms has been in-
vestigated expansively in recent years. Table I outlines limita-