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by adopting a PCPG management routine. In the following
sections we briefly describe our approach, emphasizing the
Exynos 5422 platform and PCPG based WLC interactions.
A. Performance Counter:
The Exynos 5422 big. LITTLE system on chip (SoC) board
has been chosen to validate our proposed approach, as shown
in Fig. 3(a). To activate the observing of power-performance
counter, we prepared a custom system routine compatible with
ARM’s technical specification document capable of record
diverse performance counter readings at pre-determined peri-
odic spans. This routine, along with its libraries, is presently
being intended for open release. In this work, performance
counter is adopted to report system performance events in-
cluding, instruction retired cache misses, and cycles. Further,
it is used to monitor temperature, current, voltage, and power
from the sensors in the Odroid-XU3 board by adopting the
approach provided by Walker et al. [29]. In this work, the
low activity class which leads to the significant dark silicon
power consumption, as the supply voltage and clock remain
operational, has been captured for different PCPG scenarios
and frequencies.
The two observations below can be summarized as follows.
Primarily, as the number of dark silicon related cores increase
(big or LITTLE) the power consumption will drastically in-
crease. For instance, the power consumption of 4 big idle
cores at 2 GHz is about 1.5 Watt, which decreases to roughly
0.6 Watt when only one big core acts as dark silicon area.
Secondly, the dark silicon related power consumption is also
reliant on the clock frequency. As an example, when parallel
threads of cannel application are assigned to LITTLE cores
only, the dark silicon related power consumption of the idle
four big cores increases from about 0.6 Watt at 1400 MHz to
almost 1.5 Watt at 2 GHz.
B. Power Gating Management and PSN:
The proposed runtime PCPG based WLC coupled with DVFS
control is performed according to Algorithm I. This algorithm
specifies the type of the workload, number of PCPG, and
DVFS combinations for any exercised application. This can
be achieved through comparing observed reading from perfor-
mance counter to pre-set thresholds acquired from offline ex-
periments at design time. Depending on extensive experiment
from [11] [19], we categorize workloads by their process-
ing demands (CPU) and communication intensive (memory).
Therefore, workloads can be classified into three categories:
memory-intensive (MI), CPU-intensive (CI), and mix of CPU
and memory-intensive (MIX).
A number of flag registers, on every time interval, are modified exercised, compared to the ondemand governor and previous
by the system software routine relying on the number of dark
silicon cores. For instance, when two big cores (core 4 and
core 5) are acted as dark silicon area the corresponding flag
Alrudainy, Marzook, Hussein & Shafik
DVFSDetermine: Compute: Monitors:
1-Application class Classification 1-Performance counter
(a) Hardware description of (b) PCPG based2-PCPG and DVFS2-Power
Exynos 5422 big.LITTLE WLC metricsmetrics
TM
PCPG management + Power switch network using CMOS
PCPG PCPG
512k L2-Cashe 2M L2-Cashe with ECC
128-bit AMBAACE Coherent Bus Interface
DRAM LPDDR3(933MHz)14.9 Gbytes/s
Fig. 3. (a) Hardware description of Samsung Odroid-XU3
platform; (b) Proposed PCPG based WLC metrics .
bits are assigned to 1 highlighting the advantages of power
gating. These bits can then be adopted to activate the PSN
based CMOS transistors, thereby shutting down those dark
silicon related cores. In this work, PSN has been designed
using Cadence Virtuoso tool box at 45nm technology node.
Practically, the maximum current drawn when CPU-intensive
workload is exercised on the A15 core has been reported to
be Imax=1A per core at f=2000 MHz. Therefore, a number
of switch transistor is connected in parallel at their maximum
width to ensure providing maximum current of 1A to the ac-
tive core [30]. The target impedance of the PSN that would
be worked over a broad of frequency band, can be calculated
by postulating a 5% allowable ripple in the core supply volt-
age, and a 50% drawn current in the rise and fall time of the
processor clock [31]:
ztarget = 0.1 ×Vdd (1)
I peak
As a result, the power consumption overhead causing by adopt-
ing the PSN has been computed using Cadence tool for fair
comparison.
VI. RESULTS
For verification purposes five different set of applications
have been adopted in this work as a case study. As expected
our PCPG based WLC achieves the highest energy efficiency
(IPS/Watt) improvement when streamcluster application is
work published in [11]. This is because streamcluster appli-
cation is a memory-intensive workload which prefer to be ex-
ercised at little cores with lower DVFS level. This indicating