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tions and contributions of the most recent existing approaches.
Over recent years significant research has been conducted
addressing real-time energy reduction approaches. These tech-
niques have taken into account single metric based optimiza-
tion: mainly performance improvement within a particular
power budget, or performance-constrained for power reduc-
tion [14]. For instance, real-time dynamic voltage frequency
scaling (DVFS) control method for power reduction of many-
core embedded platforms has been proposed in [15, 21–23].
Their method utilizes performance and user experience con-
straints to obtain the minimum DVFS combinations by adopt-
ing reinforcement learning and transfer principles. Others
illustrated another power reduction method that models real-
time workload analysis to constantly maintain the core allo-
cations and DVFS combination through predictive controls
using multinomial logic regression [16]. A number of re-
search papers have also demonstrated analytical investiga-
tions adopting simulation frameworks, including McPAT, and
gem5. These studies have utilized task mapping, DVFS, and
offline optimization methods to significantly reduce the power
dissipation under workloads variations [17, 24–26]. A novel
work in [11] presented low complexity runtime management
approach based on workload classification for heterogeneous
many core platforms. This approach addresses most config-
uration space of odroid-xu3 platform including core types,
threads allocation, optimum dynamic voltage and frequency
scaling.
A hardware based load balancing scheme for homogeneous
many-core system is assessed in aspect of power consumption
and thermal behavior [7]. In this scheme, a power minimiza-
tion is reached by powering off the dark silicon area. In [8],
to minimize static power consumption during the sub-clock
cycle, a power gating based sub-clock approach was imple-
mented in ARM Cortex-M0 processor. In the same context,
Charles et al. [9] performed per core power gating (PCPG)
in contemporary homogeneous Intel Core i7 processor. It is
illustrated that additional power headroom can be transferred
to the active cores by power gating dark silicon area, idle
cores, to boost their frequency and voltage without overstep
the thermal and power envelop. Likewise, transferring energy
saving from dark silicon area into enabled cores was studied
in [10] using a homogeneous many core platforms named as
AMD Opteron 6168. The practical outcomes of this work
are relied on manually adjustment of dynamic voltage scaling
(DVS) combination integrated with per core power gating
approach.
Alrudainy, Marzook, Hussein & Shafik
III. SYSTEM ARCHITECTURE AND
APPLICATIONS
The impetus of adopting heterogeneous architectures, com-
prising two or various types of CPUs, is recently increasing.
Although these platforms provide superior performance, it
is essential to ensure optimum energy consumption while
exercising various types of workloads. The Odroid-XU3
board facilitates approaches including affinity, DVFS, and
core manually disabling, normally utilized to enhance sys-
tem operation in respect of energy consumption and perfor-
mance. The Odroid-XU3 board is a small heterogeneous
8-cores computational platform. This board can run Android
4.4 or Ubuntu 14.04 operating systems. The primary element
of Odroid-XU3 board is the 28 nm Application Processor
Exynos 5422. The main processor architecture depicted in
Fig. 1. This multiprocessor system on chip (MPSoC) is de-
veloped by ARM big.LITTLE heterogeneous architecture and
comprises of a low power Cortex-A7 quad core block, a high
performance Cortex-A15 quad core processor block, 2GB
DRAM LPDDR3, and a Mali-T628 GPU. Further, this board
comprises of 4 real time current sensors that provide the op-
portunity to measure power consumption on the 4 separated
power blocks: little (A7) CPUs, big (A15) CPUs, DRAM,
and GPU. In addition, there are also 1 temperature sensor
for the GPU and 4 temperature sensor for each of the A15
CPUs. The clock frequency and supply voltage (Vdd) of the
Odroid-XU3 board, for each power block, can be adjusted
using a range of pre-defined range of values. For example, the
low power Cortex-A7 quad core block has a set of frequencies
ranged between 200 MHz and 1400 MHz with a step size of
100 MHz, while the performance Cortex-A15 quad core block
features a set of frequencies ranged between 200 MHz and 2
GHz with a step size equal to 100MHz.
The PARSEC real application benchmark suite supports
both emerging and current workloads for multi processing
hardware [27]. It contains a various set of workloads from
diverse domains including systems applications or interactive
animation that mimic large-scale commercial workloads. In
our paper, Therefore, PARSEC applications has been adopted
and exercised on the Odroid-XU3 system on chip (SoC) whose
TABLE II.
CHARACTERISTIC OF PARSEC BENCHMARK [27]
Application Domain Type
ferret Similarity Search CPU
cannel CPU
Engineering CPU+mem
bodytrack Computer Vision mem
streamcluster mem
fluidanimate Data Mining
Animation