Page 279 - 2024-Vol20-Issue2

Received: 5 August 2024 | Revised: 13 Septemper 2024 | Accepted: 14 September 2024

DOI: 10.37917/ijeee.20.2.24 Vol. 20 | Issue 2 | December 2024

Open Access

Iraqi Journal for Electrical and Electronic Engineering

Original Article

Understanding Power Gating Mechanism Based on

Workload Classification of Modern Heterogeneous

Many-Core Mobile Platform in the Dark Silicon Era

Haider Alrudainy*1, Ali K. Marzook2, Muaad Hussein1, Rishad Shafik3
1Basra Technical Engineering College, Southern Technical University, Basra, Iraq

2School of Electrical Engineering, Basra University, Basra, Iraq
3School of EEE, University of Newcastle, Newcastle upon Tyne, UK

Correspondance
*Haider Alrudainy
Electronic Department,
Basra Technical Institute, Basra, Iraq
Email: h.m.a.alrudainy@stu.edu.iq

Abstract
The rapid progress in mobile computing necessitates energy efficient solutions to support substantially diverse and
complex workloads. Heterogeneous many core platforms are progressively being adopted in contemporary embedded
implementations for high performance at low power cost estimations. These implementations experience diverse
workloads that offer drastic opportunities to improve energy efficiency. In this paper, we propose a novel per core power
gating (PCPG) approach based on workload classifications (WLC) for drastic energy cost minimization in the dark
silicon era. Core of our paradigm is to use an integrated sleep mode management based on workloads classification
indicated by the performance counters. A number of real applications benchmark (PARSEC) are adopted as a practical
example of diverse workloads, including memory- and CPU-intensive ones. In this paper, these applications are exercised
on Samsung Exynos 5422 heterogeneous many core system showing up to 37% to 110% energy efficient when compared
with our most recent published work, and ondemand governor, respectively. Furthermore, we illustrate low-complexity
and low-cost runtime per core power gating algorithm that consistently maximize IPS/Watt at all state space.

Keywords
Dark Silicon, Energy-efficient, Multi-core Mobile System, Per Core Power Gating, Workload Classification.

I. INTRODUCTION at 22 nm technology node 21% of a chip must be powered off.
While at 8nm technology the percentage of the dark silicon
In the recent times, the continuing demand of low energy cost portion increases drastically to more than 50% [1] [2]. Other
at desirable throughput has led to the advent of heterogynous researchers show that 64% of the total 64-core chip has been
many core mobile systems. These platforms, characterized observed as dark silicon [3–5]. Thus, it is predicted that the
by an ever rising number of cores on a single chip, provide power consumption of many core platforms will be increased
significant computational capability. However, this increasing by a factor of 10 over the next decade due to the dark silicon
number of core incorporates with a significant set of chal- phenomenon [6].
lenges, profoundly emphasized by the emergence of dark
silicon [1]. In the same context, continuing scaling the tech- Unlike homogenous many-core systems, heterogeneous
nology node according to Moore’s Law has led to reach to a many-core platforms are widely being recently adopted in
point at which large portion of the chip has to be shut down to contemporary embedded mobile implementations. This is due
avoid significant power consumption. It is demonstrated that to its superior energy efficiency at the desirable throughput

This is an open-access article under the terms of the Creative Commons Attribution License,
which permits use, distribution, and reproduction in any medium, provided the original work is properly cited.
©2024 The Authors.
Published by Iraqi Journal for Electrical and Electronic Engineering | College of Engineering, University of Basrah.

https://doi.org/10.37917/ijeee.20.2.24 |https://www.ijeee.edu.iq 275