Page 282 - 2024-Vol20-Issue2

278 | Alrudainy, Marzook, Hussein & Shafik

Fig. 1. Odroid-XU3 board comprising Samsung Exynos 5422 heterogeneous MPSoC

1B 2B 3B 4B V (volt) A7 cores A15 cores
3L 1B 3L 2B 3L 3B 3L 4B 1.3
2L 1B 2L 2B 2L 3B 2L 4B
1.2

1.1

1L 1B 1L 2B 1L 3B 1L 4B 1
1L 2L 3L 0.9
0.8 Frequency
(MHz)

200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000

(a) (b)

Fig. 2. a) number of potential core allocations of exercising single application; b) experimental data of cannel application
demonstrating the number of DVFS combination when exercised on four big (A15) and four little (A7) cores.

heterogeneity can be illustrative of various design choices CPU-intensive, respectively.
that can significantly impact workloads. PARSEC bench- DVFS of odroid-xu3 platform is enabled by the power gover-
mark suite experience diverse: data sharing patterns, work- nors at the system software layer. For example, Linux incor-
load partitions, and memory behaviors from majority other porates various power governors that can be actuated based
benchmark suites in widespread use. Table II shows the char- on the system demands. These comprise powersave for low
acteristics of PARSEC benchmark suit which are adopted in performance and low power mode, performance for higher per-
our work. Three set of applications (ferret/cannel, fluidan- formance mode, ondemand for performance-sensitive DVFS
imate/streamcluster, and bodytrack) are opted to illustrate level, and userspace for user-customized DVFS combina-
CPU-intensive, memory-intensive, and mixed memory with tion. These governors aim to appropriately adjust the volt-