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VI. CONCLUSION international conference on communication and signal
processing (ICCSP), pp. 0319–0322, IEEE, 2019.
In this work, a (24*24)-bit adjusted-Vedic multiplier (AVM)
with high speediness and low area consumption is proposed [7] K. J. Ramesh et al., “A review: Multiply and accumulate
and implemented. The utilization of an enhanced design for architectures for digital signal processing and digital
the Brent-Kung carry-select adder (EBK-CSLA) which used image processing,” Turkish Journal of Computer and
to perform the final addition has eliminated any propagation Mathematics Education (TURCOMAT), vol. 12, no. 12,
for the carry and thus, its highly reduced the delay of the pp. 3797–3804, 2021.
multiplier. Moreover, the use of the improved XOR-gate to
design the multiplier is extremely reduced the area occupa- [8] S. S. Mahakalkar and S. L. Haridas, “Design of high
tion and the delay of the design. The proposed (24*24)-bit performance ieee754 floating point multiplier using
AVM offers efficient speed and area utilization for integra- vedic mathematics,” in 2014 International Conference
tion into fast floating-point MAC module of the DSP systems. on Computational Intelligence and Communication Net-
The proposed AVM achieves reduction in delay and FPGA works, vol. 52, pp. 985–988, IEEE, 2014.
area occupation by 33.16% and 42.42%, respectively for the
unpipelined design, and reduction in delay of 44.78% for [9] G. Di Meo, G. Saggese, A. G. Strollo, D. De Caro, and
pipelined design compared with the existing designs. N. Petra, “Approximate floating-point multiplier based
on static segmentation,” Electronics, vol. 11, no. 19,
CONFLICT OF INTEREST p. 3005, 2022.
The author have no conflict of relevant interest to this article. [10] A. Kanhe, S. K. Das, and A. K. Singh, “Design and
implementation of floating point multiplier based on
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