Page 189 - 2024-Vol20-Issue2

185 |
Fig. 3. Internal organization of Single-precision
floating point MAC.
IV. PROPOSED ADJUSTED VM (AVM)
This section presents a distinctive design for a (24*24)-bit
VM based on UT-Sutra approach called here adjusted VM
(AVM) to be used for floating-point DSP’s MAC module. The
work starts by designing a (6*6)-bit AVM, then it is extended
to design (12*12)-bit and (24*24)-bit AVMs accordingly.
A. Proposed (6*6)-bit AVM.
A (6*6)-bit AVM is designed using four (3*3)-bit conventional
VMs, a single (6-bit) CSA to add three intermediate partial
products and generate two (6-bit) vectors: the sum and carry
vectors. An enhanced 6-bit Brent-Kung carry-select adder
(EBK-CSLA) has proposed and be incorporated in the AVM
design to add the resultant two vectors generated from the
CSA for producing the final product as illustrated in Fig. 4.
The 6-bit EBK-CSLA consists of two (3-bit) Brent-Kung
(BK) adders, a 4-bit binary-to-access-1 convertors (BEC1),
and a 3-bit MUX. The three MSBs of the final product can
be obtained using a 3-bit increment-by-1 convertor (IB1C)
instead of using an adder, for its high speed, since it consists This step will further improve the performance of the AVM
of fewest logic gates in comparison to with any adder.
B. Design of (24*24)-bit AVM
The (6*6)-bit AVM can be easily extended to design a (12*12)-
bit AVM. In this case, four (6*6)-bit AVM modules, a 12-bit
CSA to reduce the intermediate partial products from three
vectors to two (12-bit) vectors (namely, sum and carry), and
then, an 11-bit EBK-CSLA is used to produce the final product
bits of the intermediate stage, followed by a 6-bit EBK-CSLA
which is used to generate the most significant 6- bits of the
product, as demonstrated in Fig. 5.
Similarly, the (24*24)-bit AVM is designed from the
(12*12)-bit AVM, as illustrated in Fig. 6. The proposed
Hussein & AL-Assfor
Fig. 4. The Proposed (6*6)-bit AVM.
Fig. 5. The Proposed (12*12)-bit AVM.
(24*24)-bit AVM consists of four (12*12)-bit AVMs, followed
by a single (24-bit) CSA to reduce the partial products gener-
ated from the (12*12)-bit AVMs to two vectors: the sum (S-
vector) and the carry vector (C-vector). The S-vector consists
of 24-bit (bits S[23:00]), while the carry vector (C-vector) con-
sists of 24-bit (bits C[24:01]). The least significant bit (LSB)
of the S-vector (namely; bit S[00]) represents the 12th bit of
the final product (namely, S[00]=Pr[12]). This means that
one can minimize the size of the proposed EBK-CSLA which
is used to generate the final product bits from 24-bit to 23-bit.
design. The output of the (23-bit) EBK-CSLA represents the
product bits Pr[35:13]. Fig. 7 depicts the design of the (23-
bit) EBK-CSLA, it consists of six blocks of variable bit sizes
BK-adders along with five BEC and a set of MUXs to carry
out carry selection. To generate the most significant 12-bit of
the final product (namely, bits Pr[47:36]), two (6-bit) EBK-
CSLA modules are utilized. The two output-carry signals c1
and c2 generated from the CSA and the (23-bit) EBK-CSLA,
respectively are OR-ed together to enable the first (6-bit) EBK-
CSLA for generating the product bits Pr[41:36]. The output