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Fig. 1. The format of BSP floating-point number [8]
is consist of three filed: sign-bit (SX ), biased exponent (EX ), (24*24)-bit AVM is then, optimized using the pipelining ap-
and the mantissa (or significand (Mx = 1.FX ) [9]. Where FX is
the fraction bits of the mantissa. These three fields are packed
into a word such that.
X = (-1)SX · MX · 2EX (1)
Floating-point multiplier is used to carry out the mantissa
multiplications of two floating-point operands [10]. Multipli-
cation two (n-bit) numbers X and Y can be carried out by the
following three steps [4] :
Step 1: generation of partial-products.
Step 2: reduction these partial-products using a set of adders,
like (3:2) carry-save adders (CSA) (or simply CSA) to pro-
duce the intermediate product in sum and carry vectors form.
The (3:2) in CSA denotes the number of inputs/outputs of the
adder.
Step 3: generation the final product (final multiplication re-
sult) using fast adder. The inputs of this adder are the sum
and carry vectors produced in step 2.
Generally, the multiplier speed essentially depends on the
accumulation of the sum and carry vectors to produce the final
multiplication result and the multiplication algorithm utilized.
The goal of this work is to design high speeding and low
area VM based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra)
approach for BSP floating-point MAC modules to achieve
high-performance digital-signal processing. This goal may be
accomplished throughout the steps bellow:
- Design an efficient adder to add the intermediate sum and
carry vectors that generated from the CSA to produce the
final multiplication result, since the speed of the multiplier is point operands. Their design had based on using three cas-
highly relied on the speed of that adder.
- Usage of the improved XOR gate in [11] to design the entire
parts of the proposed multiplier, and
- Improve the speed of the proposed multiplier further using
the pipelining concept.
Based on the above steps, this work presents a distinctive
design for a (6*6)-bit VM called here adjusted-VM (simply,
AVM). The design has utilized the conventional (3*3)-bit
VM along with an enhanced design for the Brent-Kung carry-
select adder (EBK-CSLA) in [11] to produce the final product
result from the sum and carry vectors. The (6*6)-bit AVM
circuit is in turn, utilized to design (12*12)-bit and then, a
Hussein & AL-Assfor
(24*24)-bit AVM which can be utilized to fulfill the mantissa
multiplication for BSP floating-point numbers. The proposed
proach. The proposed AVM architectures are built using the
improved XOR-gate to substantially improve the multiplier
performance. The proposed AVMs are coded in VHDL, sim-
ulated in Xilinx 14.7 ISE software tool, and synthesized by
different FPGA families, such as: Virtex-5, Virtex-6, Virtex-7,
Zynq. and then, a complete analysis for their performances is
provided.
This work is arranged as follows: Sec. II. reviews some of
the previous works related to the floating-point multipliers
and MAC modules. Sec. III. , explains the general design of a
BSP floating-point MAC module. Section IV. affords details
of the proposed AVM using an EBK-CSLA architecture, after
which the details of the implementation results, simulations,
and comparing the effectiveness of the proposed multiplier
with the existent multiplier designs are offered in Sec. V. , and
the conclusion is given in Section VI. .
II. LITERATURE REVIEW
In 2015, N. Jithendra et al [12] have presented two approaches
to design MAC modules one to perform fixed-point signed
numbers and the other to perform floating-point numbers.
Their architectures were designed utilizing Wallace-tree mul-
tiplier and ripple carry adder (R-CA). Their multiplier and
MAC designs had presented enhancement in terms of power,
but gained higher delay and area consumption due to using the
Wallce tree structure and due to the utilization of the R-CA
which leads to high carry propagation delay during addition.
In 2016, authors in [13] had proposed a VM for floating-
caded carry lookahead-adders (CLA-A)s to perform the partial-
product reduction and the final addition to generate the final
product. Nevertheless, their design had consumed higher area
and had a considerable delay due to the carry propagation
among the three adders.
In [14, 15], authors had designed (24*24)-bit Vedic based
multipliers to perform mantissa multiplication for floating-
point inputs. Their designs had comprised three cascaded
levels of R-CAs to add the generated partial-products and to
produce the final product. Their designs have achieved low
speed due to using the R-CA which is considered the slowest
adder among the adders.
G. Jha et al [16] had designed four kinds of multipliers
to be used in MAC module, namely modified-booth, Wallace
tree-reduction, add-shift, and combinational array multipliers
and analyzed its performance when using these multipliers.
However, none of these multipliers have introduced good
performance in terms of power, delay and area occupation on
the designed MAC. For example, the Wallce tree-reduction