Page 190 - 2024-Vol20-Issue2

186 | Hussein & AL-Assfor

TABLE I.
PERFORMANCE RESULTS OF DIFFERENT BIT SIZE AVM

CIRCUITS

FPGA Proposed AVM
Family
Parameters (24*24)-bit
Virtex-5
No. of Virtex-6 (6*6) (12*12) unpipelined piplined
FPGA LUTs Virtex-7 -bit -bit
72
Delay(ns) Zynq 72 310 1260 568
Virtex-5 68
Virtex-6 61 306 1014 594
Virtex-7 4.88
4.82 294 962 563
Zynq 4.71
4.34 288 1014 558

7.956 12.74 3.65

7.92 12.395 3.352

7.832 11.583 2.843

Fig. 6. The Proposed architecture of a (24*24)-bit 7.074 11.583 2.58
AVM using fast 23-bit EBK-CSLA.
FPGA Virtex families are chosen for the comparison purpose
Fig. 7. Internal organization of the proposed 23-bit with previous designs, while the Zynq family is utilized for
EBK-CSLA. its high features in achieving the best performance parameters
which can be noticed clearly in Table I.

Fig. 8 demonstrates the register-transfer-level (RTL)-schematic
of the synthesized (24*24)-bit AVM. It can be noticed that the
design has utilized the following number of hardware modules:
four modules of (12*12)-bit AVM, a CSA to carry out 24-bit
addition, one (23-bit) EBK-CSLA, two (6-bit) EBK-CSLA, a
(2:1) MUX, and an OR-gate.

carry of this adder is used as a carry-in to the second (6-bit) Fig. 8. RTL- scheme of the proposed (24*24)-bit AVM
EBK-CSLA to update the final product bits (bits Pr[47:42])
by adding the six most-significant bits of the partial-product
with ‘000001’ instead of utilizing IB1C circuit.

In this work, the improved XOR-gate is utilized in de-
signing the AVM to improve its performance further. The
improved XOR-gate architecture consists of three logic gates
(namely, AND, NAND, and OR) instead of five logic gates.
To optimize the speed of the AVM more, the pipeline concept
is applied [23]. The pipeline stage can be applied either before
the CSA or within the EBK-CSLA to generate the product
bits from the multiplier faster. In this work, it is found that the
(24*24)-bit AVM designed utilizing (3x3)-bit pipelined-VM
gives the best performance results.

V. RESULTS AND DISCUSSION

All the proposed multipliers in this work, namely, the (6*6)-
bit, (b)-bit, and (24*24)-bit AVMs with/without pipelining
are coded in VHDL and their performances in terms of the
area occupation in FPGA and the delay (speed=1/delay) are
assessed in Xilinx using four FPGA families: Virtex-5, Virtex-
6, Virtex-7, and Zynq, as demonstrated in Table I. Note that the