Page 186 - 2024-Vol20-Issue2

Received: 2 June 2023 | Revised: 21 August 2023 | Accepted: 20 October 2023

DOI: 10.37917/ijeee.20.2.15 Vol. 20 | Issue 2 | December 2024

Open Access

Iraqi Journal for Electrical and Electronic Engineering

Original Article

Design Efficient Vedic-Multiplier for Floating-Point MAC

Module

Fatima Tariq Hussein*, Fatemah K. AL-Assfor
Computer Engineering Department, College of Engineering, University of Basrah, Basrah, Iraq

Correspondance
* Fatima Tariq Hussein
Department of Computer Engineering,
University of Basrah, Basrah, Iraq
Email: pgs.fatima.tariq@uobasrah.edu.iq

Abstract
Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such
as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy.
The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a
distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module
to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and
utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit
AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM.
Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed
(24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP)
floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by
Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in
delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined
design, and a reduction in delay of 44.78% compared with the existing pipelined design.

Keywords
Multiplier-Accumulator (MAC), Enhanced Brent-Kung Carry-Select Adder (EBK-CSLA), Adjusted Vedic multiplier
(AVM), Carry Save Adder (CSA).

I. INTRODUCTION multiplier performance. Multiplication of two floating-point
numbers can be accomplished using various multipliers and
Multiply-Accumulated (MAC) module is considered the most exploiting diverse algorithms. Vedic multiplier (VM) is con-
important module in digital signal processor (DSP), multi- sidered as one of the most important multipliers for its good
media information processing, microprocessors systems and efficiency in terms of high speed [3–6]. The floating-point is
hence, it has a considerable effect on their performance in a data structure utilized to exemplify real numbers in a binary
terms of speed and area occupancy [1]. MAC module can form. The IEEE-754 Standard floating-point numbers encom-
be employed for both fixed-point and floating-point compu- passes two basics binary formats, namely single-precision (32-
tations. Floating-point arithmetic is widely utilized in DSP bit) and double precision (64-bit),that comprise arithmetic op-
applications like, filters, correlation, convolution and image erations and round mechanisms [7]. IEEE-754 binary single-
processing applications to attain higher accuracy. A MAC precision (BSP) and binary double-precision (BDP)formats
module is comprised of an (n*n) multiplier and a (2n+c) ac- are widely utilized in MAC modules. Fig. 1 illustrates the
cumulated adder, with c symbolizes the extra bits to avert implementation of the BSP-floating-point operand (X) [8]. It
overflow case [2]. MAC performance mainly relies on its

This is an open-access article under the terms of the Creative Commons Attribution License,
which permits use, distribution, and reproduction in any medium, provided the original work is properly cited.
©2024 The Authors.
Published by Iraqi Journal for Electrical and Electronic Engineering | College of Engineering, University of Basrah.

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