Audio encryption has gained popularity in a variety of fields including education, banking over the phone, military, and private audio conferences. Data encryption algorithms are necessary for processing and sending sensitive information in the context of secure speech conversations. In recent years, the importance of security in any communications system has increased. To transfer data securely, a variety of methods have been used. Chaotic system-based encryption is one of the most significant encryption methods used in the field of security. Chaos-based communication is a promising application of chaos theory and nonlinear dynamics. In this research, a chaotic algorithm for the new chaotic chameleon system was proposed, studied, and implemented. The chameleon chaotic system has been preferred to be employed because it has the property of changing from self-excited (SA) to hidden-attractor (HA) which increases the complexity of the system dynamics and gives strength to the encryption algorithm. A chaotic chameleon system is one in which, depending on the parameter values, the chaotic attractor alternates between being a hidden attractor and a self-excited attractor. This is an important feature, so it is preferable to use it in cryptography compared to other types of chaotic systems. This model was first implemented using a Field Programmable Gate Array (FPGA), which is the first time it has been implemented in practical applications. The chameleon system model was implemented using MATLAB Simulink and the Xilinx System Generator model. Self-excited, hidden, and coexisting attractors are shown in the proposed system. Vivado software was used to validate the designs, and Xilinx ZedBoard Zynq-7000 FPGA was used to implement them. The dynamic behavior of the proposed chaotic system was also studied and analysis methods, including phase portrait, bifurcation diagrams, and Lyapunov exponents. Assessing the quality of the suggested method by doing analyses of many quality measures, including correlation, differential signal-to-noise ratio (SNR), entropy, histogram analysis, and spectral density plot. The numerical analyses and simulation results demonstrate how well the suggested method performs in terms of security against different types of cryptographic assaults.
In medium voltage and high-power drive applications, pulse width modulation (PWM) techniques are widely used to achieve effective speed control of AC motors. In real-time, an industrial drive system requires reduced hardware complexity and low computation time. The reliability of the AC drive can be improved with the FPGA (field programmable gate array) hardware equipped with digital controllers. To improve the performance of AC drives, a new FPGA-based Wavect real-time prototype controller (Xilinx ZYNQ-7000 SoC) is used to verify the effectiveness of the controller. These advanced controllers are capable of reducing computation time and enhancing the drive performance in real- time applications. The comparative performance analysis is carried out for the most commonly used voltage source inverter (VSI)-based PWM techniques such as sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) for three-phase, two-level inverters. The comparative study shows the SVPWM technique utilizes DC bus voltage more effectively and produces less harmonic distortion in terms of higher output voltage, flexible control of output frequency, and reduced harmonic distortion at output voltage for motor control applications. The simulation and hardware results are verified and validated by using MATLAB/Simulink software and FPGA-based Wavect real-time controller respectively.
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.
This article emphasizes on a strategy to design a Super Twisting Sliding Mode Control (STSMC) method. The proposed controller depends on the device of Field Programmable Gate Array (FPGA) for controlling the trajectory of robot manipulator. The gains of the suggested controller are optimized using Chaotic Particle Swarm Optimization (PSO) in MATLAB toolbox software and Simulink environment. Since the control systems speed has an influence on their stability requirements and performance, (FPGA) device is taken in consideration. The proposed control method based on FPGA is implemented using Xilinx block sets in the Simulink. Integrated Software Environment (ISE 14.7) and System Generator are employed to create the file of Bitstream which can be downloaded in the device of FPGA. The results show that the designed controller based of on the FPGA by using System Generator is completely verified the effectiveness of controlling the path tracking of the manipulator and high speed. Simulation results explain that the percentage improvement in the Means Square Error (MSEs) of using the STSMC based FPGA and tuned via Chaotic PSO when compared with the same proposed controller tuned with classical PSO are 17.32 % and 13.98 % for two different cases of trajectories respectively.
Recently, chaos theory has been widely used in multimedia and digital communications due to its unique properties that can enhance security, data compression, and signal processing. It plays a significant role in securing digital images and protecting sensitive visual information from unauthorized access, tampering, and interception. In this regard, chaotic signals are used in image encryption to empower the security; that’s because chaotic systems are characterized by their sensitivity to initial conditions, and their unpredictable and seemingly random behavior. In particular, hyper-chaotic systems involve multiple chaotic systems interacting with each other. These systems can introduce more randomness and complexity, leading to stronger encryption techniques. In this paper, Hyper-chaotic Lorenz system is considered to design robust image encryption/ decryption system based on master-slave synchronization. Firstly, the rich dynamic characteristics of this system is studied using analytical and numerical nonlinear analysis tools. Next, the image secure system has been implemented through Field-Programmable Gate Arrays (FPGAs) Zedboard Zynq xc7z020-1clg484 to verify the image encryption/decryption directly on programmable hardware Kit. Numerical simulations, hardware implementation, and cryptanalysis tools are conducted to validate the effectiveness and robustness of the proposed system.
Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.
Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.
This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation studies of speed control of a D.C. motor are conducted and the effect of a sudden change in reference speed and load are also included.