Cover
Vol. 20 No. 2 (2024)

Published: December 31, 2024

Pages: 182-189

Original Article

Design Efficient Vedic-Multiplier for Floating-Point MAC Module

Fatima Tariq Hussein 1 Fatemah K. AL-Assfor
1Computer Engineering Department, College of Engineering, University of Basrah, Basrah, Iraq
History
  • Received: June 2, 2023
  • Revised: August 21, 2023
  • Accepted: October 20, 2023
  • Available Online: July 14, 2024
DOI

https://doi.org/10.37917/ijeee.20.2.15

Abstract

Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.

Keywords

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