Cover
Vol. 14 No. 2 (2018)

Published: December 31, 2018

Pages: 108-119

Original Article

Reduced Area and Low Power Implementation of FFT/IFFT Processor

Shefa A. Dawwd 1 Suha. M. Nori
1Computer Engineering Department University of Mosul Mosul-Iraq
History
  • Received: October 31, 2018
  • Available Online: December 31, 2018
DOI

https://doi.org/10.37917/ijeee.14.2.3

Abstract

The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.

Keywords

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