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Go to Editorial ManagerHigh speed and area reduction of the Arithmetic-Logic Unit (ALU) have a fundamental role in modern processors, especially in digital signal processor (DSP). In this paper, a new elastic fixed-point (Fx-P) ALU module is proposed to perform multiple operations on real and complex numbers. The arithmetic part of the ALU executes operations such as addition, subtraction, increment, decrement, and multiplication on real numbers. For complex operands, the proposed ALU executes three operations comprising addition, subtraction, complex conjugate of complex numbers. The logical part performs the basic operations including AND, OR, NAND, NOR, XOR, XNOR, NOT and BUFFER operations. The proposed design is based on utilizing an enhanced design of a hybrid adder consists of a Han Carlson adder with a carry-select adder (EHC-CSLA) and an improved design of the Vedic multiplier to achieve multiplication operation of real numbers. A 16-bit and a 32-bit EHC-CSLA are designed first to perform real/complex addition-and- subtraction on both data types. Then, an improved-Vedic multiplier (IVM) is designed to perform multiplication on two real operands. The proposed EHC-CSLAs, numerous bit-sizes of the IVMs, and the elastic design of real/ complex ALU modules in this work are coded in VHDL, simulated, and synthesized by Xilinx ISE14.7 tool on different FPGA families. The performance results demonstrate appreciable reductions in delay and area usage in comparison to the most counterpart multipliers and ALU designs.
Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.
Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode MAC block supports three modes of operation; single 64-bit MAC operation, dual 32-bit multiplication with 32-bit single addition, and single 32-bit MAC operation. The design has utilized an adjusted architecture for the Vedic-multiplier (Adjusted-VM), a 64-bit HBK-CSLA, and a control circuit to select the desired mode of operation. The performance of the multi-mode MAC is then optimized by exploiting pipelining concept. The proposed architectures are synthesized in various FPGA families utilizing VHDL language in Xilinx ISE14.7 tool. The performance results have exposed that the proposed 64-bit I-MAC block have attained observable lessen 9.767% in delay and area usage of 47.49% compared with the most existing MAC block designs.