Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.
In the last couple decades, several successful steganography approaches have been proposed. Least Significant Bit (LSB) Insertion technique has been deployed due to its simplicity in implementation and reasonable payload capacity. The most important design parameter in LSB techniques is the embedding location selection criterion. In this work, LSB insertion technique is proposed which is based on selecting the embedding locations depending on the weights of coefficients in Cosine domain (2D DCT). The cover image is transformed to the Cosine domain (by 2D DCT) and predefined number of coefficients are selected to embed the secret message (which is in the binary form). Those weights are the outputs of an adaptive algorithm that analyses the cover image in two domains (Haar and Cosine). Coefficients, in the Cosine transform domain, with small weights are selected. The proposed approach is tested with samples from the BOSSbase, and a custom-built databases. Two metrics are utilized to show the effectiveness of the technique, namely, Root Mean Squared Error (RMSE), and Peak Signal-to-Noise Ratio (PSNR). In addition, human visual inspection of the result image is also considered. As shown in the results, the proposed approach performs better, in terms of (RMSE, and PSNR) than commonly employed truncation and energy based methods.
Adaptive filtering constitutes one of the core technologies in digital signal processing and finds numerous application areas in science as well as in industry. Adaptive filtering techniques are used in a wide range of applications such as noise cancellation. Noise cancellation is a common occurrence in today telecommunication systems. The LMS algorithm which is one of the most efficient criteria for determining the values of the adaptive noise cancellation coefficients are very important in communication systems, but the LMS adaptive noise cancellation suffers response degrades and slow convergence rate under low Signal-to- Noise ratio (SNR) condition. This paper presents an adaptive noise canceller algorithm based fuzzy and neural network. The major advantage of the proposed system is its ease of implementation and fast convergence. The proposed algorithm is applied to noise canceling problem of long distance communication channel. The simulation results showed that the proposed model is effectiveness.
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.