This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation studies of speed control of a D.C. motor are conducted and the effect of a sudden change in reference speed and load are also included.
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.
In this paper, a two-dimensional (2-D) circular-support wavelet transform (2-D CSWT) is presented. 2-D CSWT is a new geometrical image transform, which can efficiently represent images using 2-D circular spectral split schemes (circularly- decomposed frequency subspaces). 2-D all-pass functions and lattice structure are used to produce 1-level circular symmetric 2-D discrete wavelet transform with approximate linear phase 2-D filters. The classical one-dimensional (1-D) analysis Haar filter bank branches H 0 (z) and H 1 (z) which work as low-pass and high-pass filters, respectively are transformed into their 2-D counterparts H 0 (z 1 ,z 2 ) and H 1 (z 1 ,z 2 ) by applying a circular-support version of the digital spectral transformation (DST). The designed 2-D wavelet filter bank is realized in a separable architecture. The proposed architecture is simulated using Matlab program to measure the deflection ratio (DR) of the high frequency coefficient to evaluate its performance and compare it with the performance of the classical 2-D wavelet architecture. The correlation factor between the input and reconstructed images is also calculated for both architectures. The FPGA (Spartan-3E) Kit is used to implement the resulting architecture in a multiplier-less manner and to calculate the die area and the critical path or maximum frequency of operation. The achieved multiplier-less implementation takes a very small area from FPGA Kit (the die area in 3-level wavelet decomposition takes 300 slices with 7% occupation ratio only at a maximum frequency of 198.447 MHz).