Ad-Hoc networks have an adaptive architecture, temporarily configured to provide communication between wireless devices that provide network nodes. Forwarding packets from the source node to the remote destination node may require intermediate cooperative nodes (relay nodes), which may act selfishly because they are power-constrained. The nodes should exhibit cooperation even when faced with occasional selfish or non-cooperative behaviour from other nodes. Several factors affect the behaviour of nodes; those factors are the number of packets required to redirect, power consumption per node, and power constraints per node. Power constraints per node and grade of generosity. This article is based on a dynamic collaboration strategy, specifically the Generous Tit-for-Tat (GTFT), and it aims to represent an Ad-Hoc network operating with the Generous Tit-for-Tat (GTFT) cooperation strategy, measure statistics for the data, and then analyze these statistics using the Taguchi method. The transfer speed and relay node performance both have an impact on the factors that shape the network conditions and are subject to analysis using the Taguchi Method (TM). The analyzed parameters are node throughput, the amount of relay requested packets produced by a node per number of relays requested packets taken by a node, and the amount of accepted relay requested by a node per amount of relay requested by a node. A Taguchi L9 orthogonal array was used to analyze node behaviour, and the results show that the effect parameters were number of packets, power consumption, power constraint of the node, and grade of generosity. The tested parameters influence node cooperation in the following sequence: number of packets required to redirect (N) (effects on behaviour with a percent of 6.8491), power consumption per node (C) (effects on behaviour with a percent of 0.7467), power constraints per node (P) (effects on behaviour with a percent of 0.6831), and grade of generosity (ε) (effects on behaviour with a percent of 0.4530). Taguchi experiments proved that the grade of generosity (GoG) is not the influencing factor where the highest productivity level is, while the number of packets per second required to redirect also has an impact on node behaviour.
CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.
Energy consumption problems in wireless sensor networks are an essential aspect of our days where advances have been made in the sizes of sensors and batteries, which are almost very small to be placed in the patient's body for remote monitoring. These sensors have inadequate resources, such as battery power that is difficult to replace or recharge. Therefore, researchers should be concerned with the area of saving and controlling the quantities of energy consumption by these sensors efficiently to keep it as long as possible and increase its lifetime. In this paper energy-efficient and fault-tolerance strategy is proposed by adopting the fault tolerance technique by using the self-checking process and sleep scheduling mechanism for avoiding the faults that may cause an increase in power consumption as well as energy-efficient at the whole network. this is done by improving the LEACH protocol by adding these proposed strategies to it. Simulation results show that the recommended method has higher efficiency than the LEACH protocol in power consumption also can prolong the network lifetime. In addition, it can detect and recover potential errors that consume high energy.
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.
With the substantial growth of mobile applications and the emergence of cloud computing concepts, therefore mobile Cloud Computing (MCC) has been introduced as a potential mobile service technology. Mobile has limited resources, battery life, network bandwidth, storage, and processor, avoid mobile limitations by sending heavy computation to the cloud to get better performance in a short time, the operation of sending data, and get the result of computation call offloading. In this paper, a survey about offloading types is discussed that takes care of many issues such as offloading algorithms, platforms, metrics (that are used with this algorithm and its equations), mobile cloud architecture, and the advantages of using the mobile cloud. The trade-off between local execution of tasks on end-devices and remote execution on the cloud server for minimizing delay time and energy saving. In the form of a multi-objective optimization problem with a focus on reducing overall system power consumption and task execution latency, meta-heuristic algorithms are required to solve this problem which is considered as NP-hardness when the number of tasks is high. To get minimum cost (time and energy) apply partial offloading on specific jobs containing a number of tasks represented in sequences of zeros and ones for example (100111010), when each bit represents a task. The zeros mean the task will be executed in the cloud and the ones mean the task will be executed locally. The decision of processing tasks locally or remotely is important to balance resource utilization. The calculation of task completion time and energy consumption for each task determines which task from the whole job will be executed remotely (been offloaded) and which task will be executed locally. Calculate the total cost (time and energy) for the whole job and determine the minimum total cost. An optimization method based on metaheuristic methods is required to find the best solution. The genetic algorithm is suggested as a metaheuristic Algorithm for future work.
Quantum-dot Cellular Automata (QCA) is a new emerging technology for designing electronic circuits in nanoscale. QCA technology comes to overcome the CMOS limitation and to be a good alternative as it can work in ultra-high-speed. QCA brought researchers attention due to many features such as low power consumption, small feature size in addition to high frequency. Designing circuits in QCA technology with minimum costs such as cells count and the area is very important. This paper presents novel structures of D-latch and D-Flip Flop with the lower area and cell count. The proposed Flip-Flop has SET and RESET ability. The proposed latch and Flip-Flop have lower complexity compared with counterparts in terms of cell counts by 32% and 26% respectively. The proposed circuits are designed and simulated in QCADesigner software.
The main purpose of using the suspension system in vehicles is to prevent the road disturbance from being transmitted to the passengers. Therefore, a precise controller should be designed to improve the performances of suspension system. This paper presents a modeling and control of the nonlinear full vehicle active suspension system with passenger seat utilizing Fuzzy Model Reference Learning Control (FMRLC) technique. The components of the suspension system are: damper, spring and actuator, all of those components have nonlinear behavior, so that, nonlinear forces that are generated by those components should be taken into account when designed the control system. The designed controller consumes high power so that when the control system is used, the vehicle will consume high amount of fuel. It notes that, when vehicle is driven on a rough road; there will be a shock between the sprung mass and the unsprung mass. This mechanical power dissipates and converts into heat power by a damper. In this paper, the wasted power has reclaimed in a proper way by using electromagnetic actuator. The electromagnetic actuator converts the mechanical power into electrical power which can be used to drive the control system. Therefore, overall power consumption demand for the vehicle can be reduced. When the electromagnetic actuator is used three main advantages can be obtained: firstly, fuel consumption by the vehicle is decreased, secondly, the harmful emission is decreases, therefore, our environment is protected, and thirdly, the performance of the suspension system is improved as shown in the obtained results.
Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.