Cover
Vol. 16 No. 1 (2020)

Published: June 30, 2020

Pages: 85-98

Original Article

Optimizing the Performance of MOS Stacks

Sherif M. Sharroush 1
1Electrical-Engineering Department, Faculty of Engineering, Port Said University, Port Said, Egypt
History
  • Received: April 29, 2020
  • Revised: May 27, 2020
  • Accepted: May 28, 2020
  • Available Online: May 18, 2020
DOI

https://doi.org/10.37917/ijeee.16.1.11

Abstract

CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

Keywords

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