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Go to Editorial ManagerCMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.
Radio frequency integrated circuits (RFICs) are widely used in wireless technology systems. Low-noise amplifiers, especially in the 5 GHz frequency range, are vital parts of contemporary wireless communication systems. Research on 5 GHz low-noise amplifiers aims to improve the performance of these amplifiers by addressing issues related to noise, gain, and power efficiency. Low-noise amplifiers are used in many different applications and are essential for developing more effective, efficient, and balanced wireless communication systems. The paper presents a wideband low-noise amplifier (LNA) implemented in a 5 GHz (Low-Noise Amplifier) for 5G Wi-Fi applications. It is driven by a 1.8 V supply. To increase the voltage gain and reduce the power consumption, the circuit has a common source layout and is optimized to reduce the noise figure. Single-stage common source decomposition and inductive source decomposition techniques are also used to match the circuit with the source impedance. Genetic algorithm is also used to optimize the circuit operation. The genetic algorithm has been shown to significantly reduce the noise in the low-noise amplifier circuit, which greatly improves the signal quality. The algorithm has increased the gain of the circuit, making it more sensitive to signals and enhancing its ability to process diverse signals. The proposed LNA showed a total current of 2 mA and a minimum noise figure of 1.107 dB with a high voltage gain of 21.86 dB and a power consumption of 3.6 mW. I expect the proposed LNA to be suitable for 5G Wi-Fi applications in the GHz band.