Page 115 - 2024-Vol20-Issue2

111 | Maddu & Bhasme

Fig. 7. Hardware HDL block implementation of VSI based on closed-loop control of Induction Motor

TABLE II.
WCU200 TECHNICAL SPECIFICATION

Parameter Specification details

SoC Xilinx ZYNQ-7000 SoC Dual ARM Cortex-A9 MPCore NEON Processing/FPU Engines Artix-7 Programmable FPGA

Memory 512 MB DDR3 256 Mb Quad-SPI Flash

Voltage Sensor +/-1000V Measuring Range 4 to 16 Isolated Input Channels 16 Bit A/D Conversion

Current Sensor 25A RMS +/-85A Measuring Range Closed-loop Fluxgate Sensor 4 to 16 Isolated Inputs Channels 16 Bit A/D Conversion

PWM Output 12 to 60 Outputs 15V Voltage Level

Encoder Interface Dual Encoder Interface
Relay Interface 4 NO/NC Outputs

Digital Inputs 4 Inputs(5V) with protection

Analog Outputs +/-10V Output Range Eight Output Channels 16-Bit Resolution

Connectivity 1Gigabit Ethernet

Dimension Approx. 480 x 400 x 175 mm