Search Results for enhanced-hybrid-adder-eha-

Abstract

High speed and area reduction of the Arithmetic-Logic Unit (ALU) have a fundamental role in modern processors, especially in digital signal processor (DSP). In this paper, a new elastic fixed-point (Fx-P) ALU module is proposed to perform multiple operations on real and complex numbers. The arithmetic part of the ALU executes operations such as addition, subtraction, increment, decrement, and multiplication on real numbers. For complex operands, the proposed ALU executes three operations comprising addition, subtraction, complex conjugate of complex numbers. The logical part performs the basic operations including AND, OR, NAND, NOR, XOR, XNOR, NOT and BUFFER operations. The proposed design is based on utilizing an enhanced design of a hybrid adder consists of a Han Carlson adder with a carry-select adder (EHC-CSLA) and an improved design of the Vedic multiplier to achieve multiplication operation of real numbers. A 16-bit and a 32-bit EHC-CSLA are designed first to perform real/complex addition-and- subtraction on both data types. Then, an improved-Vedic multiplier (IVM) is designed to perform multiplication on two real operands. The proposed EHC-CSLAs, numerous bit-sizes of the IVMs, and the elastic design of real/ complex ALU modules in this work are coded in VHDL, simulated, and synthesized by Xilinx ISE14.7 tool on different FPGA families. The performance results demonstrate appreciable reductions in delay and area usage in comparison to the most counterpart multipliers and ALU designs.