Page 124 - IJEEE-2023-Vol19-ISSUE-1

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associated with less harmonic distortion and less
electromagnetic interference.
There are a number of benefits to using a multilevel inverter 12- LEVEL 11 (S2 S3 S7 =ON)
for high switching frequency pulse width modulation
(PWM) as opposed to a traditional two-level inverter [14-
15].
The following are some of the more appealing aspects of a
multilayer inverter:
• Low distortion and dv/dt stress can be used to generate
the output voltage.
• The input current has a minimal distortion.
• The common mode voltage is really low.
• It has a low switching frequency.
Power switching devices and capacitor voltage sources are
the structural backbone of multilevel inverters.
Due to their capacity to measure output voltage with greater
harmonics, high voltages can be achieved with the maximum
device rating, making them suited for high-voltage
applications and voltage waveforms.
In this paper, a 15-level inverter has been suggested. The
suggested multilevel inverter employs fewer switches, is
more efficient, and generates fewer losses. Pulse width
modulation (PWM) techniques are now widely used due to
their low processing requirements, simplicity, and
resilience.
The firing pulses for the switching devices are used in a
particular PWM technique described in this research to
produce a 15-level output voltage. As a reference, one sine
waveform source is used in this procedure.
II. CIRCUIT DESCRIPTION OF PROPOSED 15-LEVEL
INVERTER
Figure 1 shows the 15-level inverter. The circuit composed
of H-Bridge devices with a three DC sources (V1, V2, and
V3). Each source connected to the circuit through a
switching device (S5, S6, and S7).
In order to understand the operation of the circuit, the
operation mode for each output level is describe as
following, and since they will be repeated for the remaining
modes, just the first seven modes of operation will be
detailed for the positive half cycle:
1- LEVEL 0 (S1 S4 =ON)
2- LEVEL 1 (S1 S4 S5 =ON)
3- LEVEL 2 (S1 S4 S6 =ON)
4- L3V3L 3 (S1 S4 S5 S6 =ON)
5- LEVEL 4 (S1 S4 S7 =ON)
6- LEVEL 5 (S1 S4 S5 S7=ON)
7- LEVEL 6 (S1 S4 S6 S7 =ON)
8- LEVEL 7 (S1 S4 S5 S6 S7 =ON)
9- LEVEL 8 (S2 S3 S5 =ON)
Al-Atbee, Kadhem, Harden, & Abdulhassan
10- LEVEL 9 (S2 S3 S6 =ON)
11- LEVEL 10 (S2 S3 S5 S6 =ON)
13- LEVEL 12 (S2 S3 S5 S7 =ON)
14- LEVEL 13 (S2 S3 S6 S7 =ON)
15- LEVEL 14 (S2 S3 S5 S6 S7=ON)
V3 S7 D3
S6 S1 S3
V2
D2
S2 S4
S5 D1
V1
Fig. 1: The circuit diagram of the 15-level inverter.
III. THE PROPOSED INVERTER'S SIMULATION MODEL &
RESULT
Figure 2 shows the Matlab-Simulink model of the proposed
inverter, and Fig.3 shows the control circuit of the proposed
inverter. Fig.4 shows the timing pulses for the switching
devices of the inverter.
This multilevel inverter has three different DC sources to
choose from. The voltage that is necessary for each switch
can be obtained from its own source. Where, V1=10V,
V2=20V, V3=40 V leading to maximum voltage up to 70
Volt. The inverter consists of 3 front end devices (S5-S7)
which are connected with a three DC voltage sources.
Using a conventional sinusoidal pulse width modulation, the
H-bridge circuit's diagonal switches receive the switching
pulses in order to perform their function. When one pair of
the diagonal switches is turned on, the other switches are
turned off, and vice versa. When S1 and S4 are turned on,
the positive half of the waveform is produced, while S2 and
S3 produce the negative half of the waveform.
The gate signals for the switches are generated by comparing
a 3-phase, (12250 Hz) triangular-carrier signal to a (50 Hz)
sinusoidal reference signal in the control circuit. The pulse
width modulation approach is used for this.