This paper presents a proposed configuration of paralleling scheme PWM DC/DC buck converter. The topological structure and operation principles are presented. A Bode plot diagram technique is used to study the stability of the scheme for different values of controller parameters and with a number of parallel modules. It is found that the results are confidence, and the proposed scheme can be used in high power applications by increasing the number of parallel modules.
In this paper, optical scalable parallel and high-speed 2D data array adder for trinary signed-digit (TSD) number is proposed. The digit-decomposition-plane (DDP) coding method is used to represent the 2D TSD data arrays. The algorithm performs parallel TSD addition in constant time independent of the size of the TSD data arrays. The design describes methodology to involve two-step TSD adder. The TSD addition is expressed with several combination logic formulas that are newly derived. Optical implementation with classical optical elements is suggested for proposed TSD adder. Preliminary demonstration example is also described.