Cover
Vol. 21 No. 2 (2025)

Published: December 16, 2025

Pages: 119-128

Original Article

FPGA-Based Implementation of a Basic Background Subtraction Algorithm for Real-Time Application

Marwan Al-Yoonus 1 Dr. Saad Al-Kazzaz 2
1Electrical Engineering Department, College of Engineering, University of Mosul, Iraq
2Mechatronics Engineering Department, College of Engineering, University of Mosul, Iraq
History
  • Received: November 17, 2023
  • Revised: February 13, 2024
  • Accepted: February 23, 2024
  • Available Online: January 20, 2025
DOI

https://doi.org/10.37917/ijeee.21.2.12

Abstract

An intelligent video system’s basic function is the detection of moving objects. Moreover, real-time systems frequently pose limitations for applications involving video processing. Practically, to increase the frame rate or in the case of limited hardware resources, the real-time processing is done on an interested image segment called the region of interest (ROI). Applying the background subtraction (BGS) algorithm to this region is considered the main preprocessing operation. This paper presents a practical study for video processing based on FPGA to detect moving objects using the BGS technique. The proposed algorithm was developed using Verilog hardware description language (HDL), synthesized, and implemented in the programmable logic (PL) part of the ZYBO-7Z010CLG400-1 platform. Finite State Machine (FSM) controller method was used to design the Intellectual Property (IP) module that controls data transfer with BRAM (loading and reading) of the input and reference image. The simulation results of the timing signal sequences of the proposed IP module with the practical test of the BGS to detect several traffic signs of image size (90×90) pixels demonstrate that the module functions as intended. The system that is being presented has a latency of 13.468 nanoseconds, making it appropriate for real-time applications.

Keywords

References

  1. F. Carrizosa-Corral, A. V´azquez-Cervantes, J.-R. Montes, T. Hern´andez-D´ıaz, J. C. Solano Vargas, L. Barriga-Rodr´ıguez, J. A. Soto-Cajiga, and H. Jim´enez-Hern´andez, “Fpga-soc implementation of an ica-based background subtraction method,” International Journal of Circuit Theory and Applications, vol. 46, no. 9, pp. 1703–1722, 2018.
  2. I. Garcia and E. Guzm´an-Ram´ırez, “A fpga-based experimentation system for designing, implementing, and evaluating real-time video processing and analysis algorithms at undergraduate level,” Computer Applications in Engineering Education, vol. 27, no. 2, pp. 387–405, 2019.
  3. I. Skliarova and V. Sklyarov, FPGA-BASED hardware accelerators. Springer, 2019.
  4. P. Sikka, A. R. Asati, and C. Shekhar, “Real time fpga implementation of a high speed and area optimized harris corner detection algorithm,” Microprocessors and Microsystems, vol. 80, p. 103514, 2021.
  5. S. Wang, C. Zhang, Y. Shu, and Y. Liu, “Live video analytics with fpga-based smart cameras,” in Proceedings of the 2019 Workshop on Hot Topics in Video Analytics and Intelligent Edges, pp. 9–14, 2019.
  6. R. Kaibou, M. S. Azzaz, M. Benssalah, D. Teguig, H. Hamil, A. Merah, and M. T. Akrour, “Real-time fpga implementation of a secure chaos-based digital crypto-watermarking system in the dwt domain using co-design approach,” Journal of Real-Time Image Processing, vol. 18, no. 6, pp. 2009–2025, 2021.
  7. G. Cocorullo, P. Corsonello, F. Frustaci, L.-d.-l.-A. Guachi-Guachi, and S. Perri, “Multimodal background subtraction for high-performance embedded systems,” Journal of Real-Time Image Processing, vol. 16, pp. 1407–1423, 2019.
  8. V. P. Korakoppa, H. R. Aradhya, et al., “An area efficient fpga implementation of moving object detection and face detection using adaptive threshold method,” in 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), pp. 1606–1611, IEEE, 2017.
  9. O. Barnich and M. Van Droogenbroeck, “Vibe: A universal background subtraction algorithm for video sequences,” IEEE Transactions on Image processing, vol. 20, no. 6, pp. 1709–1724, 2010.
  10. M. Benetti, M. Gottardi, T. Mayr, and R. Passerone, “A low-power vision system with adaptive background subtraction and image segmentation for unusual event detection,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3842–3853, 2018.
  11. V. Taraate, Taraate, and Meherishi, Advanced HDL synthesis and SOC prototyping. Springer, 2019.
  12. J. L. Brock, Introduction to Logic Circuits & Logic Design with Verilog. Spinger, 2019.
  13. M. Tomasi, S. Pundlik, and G. Luo, “Fpga–dsp coprocessing for feature tracking in smart video sensors,” Journal of Real-Time Image Processing, vol. 11, pp. 751– 767, 2016.
  14. D. A. Devi, N. R. Kathula, G. Kalluri, and L. S. Bondalapati, “Design and implementation of image processing application with zynq soc,” International Journal of Computing and Digital Systems, vol. 14, no. 1, pp. 377– 385, 2023.
  15. I. N. Rodrigues, C. L. S. de Melo, V. M. da Frota Botinelly, and J. P. de Oliveira, “Fpga hardware architecture with parallel data processing to detect moving objects using the background image subtraction technique,” in 2015 CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON), pp. 841–846, IEEE, 2015.
  16. X. Ren and Y. Wang, “Design of a fpga hardware architecture to detect real-time moving objects using the background subtraction algorithm,” in 2016 5th International Conference on Computer Science and Network Technology (ICCSNT), pp. 428–433, IEEE, 2016.
  17. G. Conti, M. Quintana, P. Malag´on, and D. Jim´enez, “An fpga based tracking implementation for parkinson’s patients,” Sensors, vol. 20, no. 11, p. 3189, 2020.
  18. T. Bouwmans, “Traditional and recent approaches in background modeling for foreground detection: An overview,” Computer science review, vol. 11, pp. 31– 66, 2014.
  19. S. Arivazhagan and K. Kiruthika, “Fpga implementation of gmm algorithm for background subtractions in video sequences,” in Proceedings of International Conference on Computer Vision and Image Processing: CVIP 2016, Volume 2, pp. 365–376, Springer, 2017.
  20. J. Cavanagh, Verilog HDL design examples. CRC Press, 2017.
  21. I. Grout, Digital systems design with FPGAs and CPLDs. Elsevier, 2011.